1. Field of the Invention
The present invention relates to integrated circuit (IC) layout and design, and more particularly to optimization of clock network capacitance on an IC.
2. Description of the Related Art
Present day digital ICs incorporate millions of transistor devices into a very small area. These devices switch and perform functions according to the edges of a core clock signal. The frequencies of core clock signals have recently exceeded the 1 gigahertz (GHz) threshold. At higher clock frequencies, controlling the capacitance of core clock signals becomes more difficult. The conventional technique of controlling capacitance by shielding a clock trace between two ground traces on the same layer as the clock trace becomes increasingly susceptible to capacitive coupling from signal traces unavoidably routed in layers above and below the layer containing the clock trace.
FIG. 1 is a partial top view of an IC 100 portraying the conventional method of controlling capacitance of clock trace. A clock trace 101 routed on a layer 107 was “isolated” from other signals on the same layer 107 by shielding it between two equal width ground traces 103 and 105, where each of the ground traces 103, 105 were routed equidistant from the clock trace 101. For example, the width of each ground trace 103, 105 is “W” and the distance between the signal trace 101 and each ground trace is “D”. The capacitance to ground of the clock trace 101 was a function of the width W of the ground traces 103, 105 as well as the distance D of each ground trace 103, 105 from the clock trace 101. By using equal-width ground traces 103, 105 and by placing the ground traces 103, 105 equal distances on either side of the clock trace 101, the clock trace 101 accordingly exhibited a relatively uniform capacitance per unit length for lower clock frequencies, e.g., C1=C2=C3=C4.
At lower clock frequencies, such as those below 1 GHz, the conventional technique was sufficient to control clock signal capacitance. As scaling technologies continued to enable devices to run at higher clock frequencies, however, the capacitance of the clock trace 101 became increasingly influenced by signal traces on layers above and below that have been unavoidably routed over and under the clock trace 101. This influence is illustrated by capacitances C5 and C6 developed between the clock trace 101 and a signal trace 109 routed on another layer 111 and crossing under the clock trace 101 at a crossover point 113. The capacitance to ground seen by the clock trace 101 at the crossover point 113 became greater than the capacitance to ground at other points along the clock trace 101. In particular, the capacitance to ground at the crossover point 113 is C2+C5>C1 , and C4+C6>C3. The additional capacitances are problematic at higher clock frequencies because the resistance-capacitance (RC) network characteristics of the clock trace 101 changes significantly at crossover points, such as the crossover point 113, thereby resulting in increased rise times, delays, and local clock signals that are relatively skewed as will now be described.
Turning to FIG. 2, a diagram 200 is presented illustrating how timing problems associated with local clock skews are experienced as a result of non-uniform trace capacitances. The diagram 200 shows two sequential logic blocks, logic block 1 201 and logic block 2 202 that are part of a pipelined data circuit. In such a circuit, data is provided from one logic block 201 to the next 202 in synchronization with local clock signals LCLK1 204 and LCLK2 205 that are supposed to be operating in synchronization. Data is provided from logic block 1 201 to logic block 2 202 over a data bus 203. It is intended that the data bus 203 is valid and should be latched into logic block 2 202 at point A. At point B, data is no longer valid on the data bus 203. For purposes of illustration, signal LCLK2 205 is depicted as delayed, and is thus not operating in relative synchronization with signal LCLK1 204. The skew in LCLK2 205 results from a non-uniform capacitance that is caused by a trace crossover in the vicinity of buffering logic (not shown) for LCLK2 204. Consequently, the rise and fall times of a master clock distribution signal (not shown) are increased to the extent that the buffering logic produces local clock signal LCLK2 205 as a delayed version of LCLK1 204. Hence, signal LCLK2 205 has a latching edge at point C that latches invalid data from the bus 203. FIG. 2 is only one example of the many different forms of timing problems that can arise as a result of clock skewing that is caused by non-uniform capacitances on a distributed clock signal.
Therefore, what is needed is to provide a method and apparatus for providing uniform capacitance per unit length of clock traces for routed circuits and integrated circuits (ICs), including circuits intended to be operated at higher clock frequencies.